/**====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
 sys.h
 Copyright (c) 2003 by CHIPNUTS Incorporated. All Rights Reserved.

 Revisions of sys.h
 Version		Name		Date			Description
 1.0			Tanent		07/27/2005		Initial Version  
**====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
#ifndef SYS_H
#define SYS_H 

#define ARM_44B0
#ifdef ARM_44B0

#define CHP_BYPASS_MODE

#define DEMO_GOLDENDEMO	1
#define DEMO_EVBBOARD		2
#define DEMO_PLATFORM	DEMO_EVBBOARD

#define	INTBASE			0x01e00000
#define	TIMERBASE 		0x01d50000

#define TM_CFR0		(TIMERBASE+0x00)	/*timer config register 0*/
#define TM_CFR1		(TIMERBASE+0x04)	/*timer config register 1*/
#define TM_CR		(TIMERBASE+0x08)	/*timer control reigster*/

#define TM0_CNTB	(TIMERBASE+0x0c)	/*timer0 count buffer register*/
#define TM0_CMPB	(TIMERBASE+0x10)	/*timer0 compare buffer register*/
#define TM0_CNTO	(TIMERBASE+0x14)	/*timer0 count observation register*/

#define TM1_CNTB	(TIMERBASE+0x18)	/*timer1 count buffer register*/
#define TM1_CMPB	(TIMERBASE+0x1c)	/*timer1 compare buffer register*/
#define TM1_CNTO	(TIMERBASE+0x20)	/**/

#define TM2_CNTB	(TIMERBASE+0x24)	/*timer2 count buffer register*/
#define TM2_CMPB	(TIMERBASE+0x28)	/*timer2 compare buffer register*/
#define TM2_CNTO	(TIMERBASE+0x2c)	/**/

#define TM3_CNTB	(TIMERBASE+0x30)	/*timer3 count buffer register*/
#define TM3_CMPB	(TIMERBASE+0x34)	/*timer3 compare buffer register*/
#define TM3_CNTO	(TIMERBASE+0x38)	/**/

#define TM4_CNTB	(TIMERBASE+0x3c)	/*timer4 count buffer register*/
#define TM4_CMPB	(TIMERBASE+0x40)	/*timer4 compare buffer register*/
#define TM4_CNTO	(TIMERBASE+0x44)	/**/

#define TM5_CNTB	(TIMERBASE+0x48)	/*timer5 count buffer register*/
#define TM5_CNTO	(TIMERBASE+0x4c)	/**/

/*timer control register*/
#define TM5_AUTORELD	(1<<26)		/*TIMER5 AUTO RELOAD*/
#define TM5_MUPD		(1<<25)		/*timer 5 manual update*/
#define TM5_START		(1<<24)		/*timer 5 start*/
#define TM4_AUTORELD	(1<<23)		/*TIMER4 AUTO RELOAD*/
#define TM4_OINVT		(1<<22)		/*timer 4 output inverter*/
#define TM4_MUPD		(1<<21)		/*timer 4 manual update*/
#define TM4_START		(1<<20)		/*timer 4 start*/
#define TM3_AUTORELD	(1<<19)		/*TIMER3 AUTO RELOAD*/
#define TM3_OINVT		(1<<18)		/*timer 3 output inverter*/
#define TM3_MUPD		(1<<17)		/*timer 3 manual update*/
#define TM3_START		(1<<16)		/*timer 3 start*/
#define TM2_AUTORELD	(1<<15)		/*TIMER2 AUTO RELOAD*/
#define TM2_OINVT		(1<<14)		/*timer 2 output inverter*/
#define TM2_MUPD		(1<<13)		/*timer 2 manual update*/
#define TM2_START		(1<<12)		/*timer 2 start*/
#define TM1_AUTORELD	(1<<11)		/*TIMER1 AUTO RELOAD*/
#define TM1_OINVT		(1<<10)		/*timer 1 output inverter*/
#define TM1_MUPD		(1<<9)		/*timer 1 manual update*/
#define TM1_START		(1<<8)		/*timer 1 start*/
#define DEAD_ZONE		(1<<4)		/*dead zone enable*/
#define TM0_AUTORELD	(1<<3)		/*TIMER0 AUTO RELOAD*/
#define TM0_OINVT		(1<<2)		/*timer 0 output inverter*/
#define TM0_MUPD		(1<<1)		/*timer 0 manual update*/
#define TM0_START		(1<<0)		/*timer 0 start*/

/*config 0*/
#define MCLK			64000000
#define ClockFreq		20000000	/* 20 MHz external clock */
#define PRESCALER16		15
#define PRESCALER256	255
#define TM0_MUX			0
#define TM1_MUX			(0<<4)
#define TIMERRELOAD_10MS (MCLK/(PRESCALER16+1)/2/100)	/*10 ms timer reload*/

/*interrupt register*/
#define INT_CR		(INTBASE+0x00)		/*interrupt control register*/
#define INT_PNDR	(INTBASE+0x04)		/*interupt pending register*/
#define INT_MODR	(INTBASE+0x08)		/*interrupt mode register(IRQ mode or FIQ mode)*/
#define INT_MSKR	(INTBASE+0x0c)		/*interrupt mask register*/
#define INT_IPSLVR	(INTBASE+0x10)		/*IRQ prioity of slave register*/
#define INT_IPMSTR	(INTBASE+0x14)		/*IRQ prioity of master register*/
#define INT_ICSLVR	(INTBASE+0x18)		/*Current IRQ priority of slave register*/
#define INT_ICMSTR	(INTBASE+0x1c)		/*Current IRQ priority of master register*/
#define INT_IISPR	(INTBASE+0x20)		/*IRQ interrupt service pending register*/
#define INT_IISPCR	(INTBASE+0x24)		/*IRQ interrupt service pending clear register*/
#define INT_FISPR	(INTBASE+0x38)		/*FRQ interrupt service pending register*/
#define INT_FISPCR	(INTBASE+0x3c)		/*FIQ interrupt service pending clear register*/
//#define INT_IRQVMR	(INTBASE+0x)		/*IRQ vectored mode register*/

/*interrupt bit define*/
#define INT_MSK_GLB		(1<<26)	/*global mask*/
#define INT_EINT0		(1<<25)	/*External interrupt 0. */
#define INT_EINT1		(1<<24)	/*External interrupt 1. */
#define INT_EINT2		(1<<23)	/*External interrupt 2. */
#define INT_EINT3		(1<<22)	/*External interrupt 3. */
#define INT_EINT4567	(1<<21)	/*External interrupt 4/5/6/7. */
#define INT_TICK		(1<<20)	/*RTC Time tick interrupt. */
#define INT_ZDMA0		(1<<19)	/*General DMA0 interrupt. */
#define INT_ZDMA1		(1<<18)	/*General DMA1 interrupt. */
#define INT_BDMA0		(1<<17)	/*Bridge DMA0 interrupt. */
#define INT_BDMA1		(1<<16)	/*Bridge DMA1 interrupt. */
#define INT_WDT			(1<<15)	/*Watch-Dog timer interrupt. */
#define INT_UERR01		(1<<14)	/*UART0/1 error Interrupt. */
#define INT_TIMER0		(1<<13)	/*Timer0 interrupt. */
#define INT_TIMER1		(1<<12)	/*Timer1 interrupt. */
#define INT_TIMER2		(1<<11)	/*Timer2 interrupt. */
#define INT_TIMER3		(1<<10)	/*Timer3 interrupt. */
#define INT_TIMER4		(1<<09)	/*Timer4 interrupt. */
#define INT_TIMER5		(1<<08)	/*Timer5 interrupt. */
#define INT_URXD0		(1<<07)	/*UART0 receive interrupt. */
#define INT_URXD1		(1<<06)	/*UART1 receive interrupt. */
#define INT_IIC			(1<<05)	/*IIC interrupt. */
#define INT_SIO			(1<<04)	/*SIO interrupt. */
#define INT_UTXD0		(1<<03)	/*UART0 transmit interrupt. */
#define INT_UTXD1		(1<<02)	/*UART1 transmit interrupt. */
#define INT_RTC			(1<<01)	/*RTC alarm interrupt. */
#define INT_ADC			(1<<00)	/*ADC EOC interrupt. */

/* I/O PORT */
#define IO_PCONA		(0x1d20000)
#define IO_PDATA		(0x1d20004)

#define IO_PCONB		(0x1d20008)
#define IO_PDATB		(0x1d2000c)

#define IO_PCONC		(0x1d20010)
#define IO_PDATC		(0x1d20014)
#define IO_PUPC			(0x1d20018)

#define IO_PCOND		(0x1d2001c)
#define IO_PDATD		(0x1d20020)
#define IO_PUPD			(0x1d20024)

#define IO_PCONE		(0x1d20028)
#define IO_PDATE		(0x1d2002c)
#define IO_PUPE			(0x1d20030)

#define IO_PCONF		(0x1d20034)
#define IO_PDATF		(0x1d20038)
#define IO_PUPF			(0x1d2003c)

#define IO_PCONG		(0x1d20040)
#define IO_PDATG		(0x1d20044)
#define IO_PUPG			(0x1d20048)

#define IO_SPUCR		(0x1d2004c)
#define IO_EXTINT	 	(0x1d20050)
#define IO_EXTINTPND	(0x1d20054)

#else
#define	INTBASE			0x14000000
#define	COREBASE		0x10000000
#define	TIMERBASE 		0x13000000


/* Registers ok for little & big Endian as all 4 bytes in the word are same reg */

/* Interrupt Controller register definitions */
#define IRQStatus INTBASE			/* Interrupt status - Read */
#define IRQRawStatus (INTBASE + 0x04)		/* Interrupt raw status - Read */
#define IRQEnable (INTBASE + 0x08)		/* Interrupt Enable - Read */
#define IRQEnableSet (INTBASE + 0x08)		/* Interrupt Enable set - Write */
#define IRQEnableClear (INTBASE + 0x0C)		/* Interrupt Enable clear - Write */

#define IRQSoft (INTBASE + 0x10)		/* Interrupt Soft - Write */
#define IRQSoftClear (INTBASE + 0x14)		/* Interrupt Soft - Write */

#define FIQStatus (INTBASE + 0x20)		/* Interrupt status - Read */
#define FIQRawStatus (INTBASE + 0x24)		/* Interrupt raw status - Read */
#define FIQEnable (INTBASE + 0x28)		/* Interrupt Enable - Read */
#define FIQEnableSet (INTBASE + 0x28)		/* Interrupt Enable set - Write */
#define FIQEnableClear (INTBASE + 0x2C)	/* Interrupt Enable clear - Write */

#define CM_IRQ_STAT (COREBASE+0x40)
#define CM_IRQ_RSTAT (COREBASE+0x44)
#define CM_IRQ_ENSET (COREBASE+0x48)
#define CM_IRQ_ENCLR (COREBASE+0x4c)

#define CM_SOFT_INTSET (COREBASE+0x50)
#define CM_SOFT_INTCLR (COREBASE+0x54)

#define CM_FIQ_STAT (COREBASE+0x60)
#define CM_FIQ_RSTAT (COREBASE+0x64)
#define CM_FIQ_ENSET (COREBASE+0x68)
#define CM_FIQ_ENCLR (COREBASE+0x6c)

/* Timer register definitions */
#define Timer1Load TIMERBASE			/* timer 1 load value - RW */
#define	Timer1Value (TIMERBASE + 0x04)		/* timer 1 value - Read */
#define Timer1Control (TIMERBASE + 0x08)	/* timer 1 control - RW */
#define Timer1Clear (TIMERBASE + 0x0C)		/* timer 1 clear - Write */


#define IRQ_EnableSerialPortB	0x04
#define IRQ_EnableSerialPortA	0x02
#define IRQ_EnableTimer2 	0x040
#define IRQ_EnableTimer1 	0x020

/* Timer control Register TC  : RW */
#define TC_EnableTimer		0x80
#define TC_Periodic		0x40
#define Prescale256		0x08
#define Prescale16		0x04

/* change clockfreq to 4,8,16,20,25 MHZ as appropriate default 20MHz */
#define ClockFreq  20000000		/* 20 MHz external clock */
#define TimerFreq  (ClockFreq / 16 )	/* the frequency of the timer */
#define TimerReload (TimerFreq / 100)	/* 100 times per sec */

#endif

#ifndef NULL
#define NULL 0
#endif
#ifndef UINT8
#define UINT8  unsigned char
#endif
#ifndef UINT16
#define UINT16 unsigned short
#endif
#ifndef UINT32
//////#define UINT32 unsigned int
#define UINT32 unsigned long
#endif
#ifndef WCHAR
#define WCHAR unsigned short
#endif

#define IN_UINT8(port) (*((volatile UINT8 *) (port)))
#define IN_UINT32(port) (*((volatile UINT32 *) (port)))
#define IN_UINT16(port) (*((volatile UINT16 *) (port)))

#define OUT_UINT8(port, val) (*((volatile UINT8 *)(port)) = ((UINT8)(val)))
#define OUT_UINT32(port, val) (*((volatile UINT32 *)(port)) = ((UINT32)(val)))
#define OUT_UINT16(port, val) (*((volatile UINT16 *)(port)) = ((UINT16)(val)))

#define SYS_IN_UINT8(io) (UINT8)IN_UINT8(io)
#define SYS_IN_UINT32(io) (UINT32)IN_UINT32(io)
#define SYS_IN_UINT16(io) (UINT16)IN_UINT16(io)

#define SYS_OUT_UINT8(io,val) (void)OUT_UINT8(io, (int)val)
#define SYS_OUT_UINT32(io,val) (void)OUT_UINT32(io, (int)val)
#define SYS_OUT_UINT16(io,val) (void)OUT_UINT16(io, (int)val)

#define SYS_INMASK_UINT8(io,mask) (IN_UINT8(io) & (mask))
#define SYS_INMASK_UINT32(io,mask) (IN_UINT32(io) & (mask))
#define SYS_INMASK_UINT16(io,mask) (IN_UINT16(io) & (mask))

#define SYS_OUTMASK_UINT8(io, mask, val) \
{\
	UINT8 temp;\
	(temp) = (((SYS_IN_UINT32(io)&(UINT8)(~(mask)))|((UINT8)((val) & (mask)))));\
	((void) OUT_UINT8(io, (UINT8)(temp)));\
}
  
#define SYS_OUTMASK_UINT32(io, mask, val) \
{\
	UINT32 temp;\
	(temp) = (((SYS_IN_UINT32(io)&(UINT32)(~(mask)))|((UINT32)((val) & (mask)))));\
	(void) OUT_UINT32(io, (UINT32)(temp));\
}
  
#define SYS_OUTMASK_UINT16(io, mask, val) \
{\
	UINT16 temp;\
	(temp) = (((SYS_IN_UINT16(io) & (UINT16)(~(mask)))|((UINT16)((val) & (mask)))));\
	(void) OUT_UINT16( io, (UINT16)(temp));\
}\

#define IF_MALLOC_FAIL_RETURN(i,j)  {if(!i)\
{return j;\
}}

#endif //SYS_H

